A traditional constant-on-time buck-converter regulates an output voltage by using the ripple on the output voltage as a PWM ramp signal to control the turn-on instant of the transistor that couples the input voltage to the filter inductor.
A constant-on-time buck converter may have a number of advantages over other types of power supplies. For example, a constant-on-time buck converter typically operates at a constant-frequency for steady-state loads, has high efficiency over a wide load range, requires few of any additional compensation components and responds quickly to changes in the load. Furthermore, such buck converter may transition relatively seamlessly between a pulse-width modulation mode (normal load conditions where switching frequency relatively constant) and a pulse-frequency modulation mode (heavy or light load conditions where the switching frequency increases or decreases, respectively).
FIG. 1 is a schematic diagram of a traditional constant-on time buck converter, i.e., power supply 10, and FIGS. 2A and 2B are respective plots of the voltages VOUT, Vref, and Q1drive of FIG. 1.
Referring to FIGS. 1-2B, the operation of the power supply 10 is described.
During a discharge time Toff, the transistor Q1 is deactivated and the transistor Q2 is activated such that the decaying current IL flowing through the inductor L also flows through the closed transistor Q2. As IL decays, VOUT ramps downward toward Vref as shown in FIG. 2A.
When VOUT ramps below Vref, a comparator 12 activates a one shot 14, which activates Q1 and deactivates Q2 for a predetermined “constant-on” or charge time Ton. During the charge time Ton, an increasing current IL flows from the input voltage Vin, through the transistor Q1 and the inductor L, to the filter capacitor Co and load Ro. As IL increases, VOUT ramps upward as shown in FIG. 2.
After the elapse of the predetermined charge time Ton, the one shot 14 deactivates Q1 and activates Q2 and the above-described cycle repeats.
There are two components to the ripple on VOUT.
The first component is the in-phase component, which is the voltage generated by current flowing through the equivalent series resistance (ESR) of the output filter capacitor Co. The in-phase component is in phase with the inductor current IL, because the voltage across a resistor is in phase with the current through a resistor.
The second component is the out-of-phase component, which is generated by the charging and discharging of the output filter capacitor Co. The out-of-phase component is out of phase with the inductor current IL, because the phase of the voltage across a capacitor lags the phase of the current through the capacitor.
Therefore, as discussed below, the value of the ESR affects the stability of the feedback loop of the power supply 10.
Generally, the loop is stable where fESR≦fSW/π, where fSW=1/(Ton+Toff)(the switching frequency), and fESR=1/(2π·ESR·Co).
Consequently, as long as both the ESR and output filter capacitor Co are relatively large (e.g. ESR≧40 milliohms (mΩ)) then the in-phase component of the ripple on VOUT is the dominant component, and thus the phase shift of the ripple relative to the inductor current IL is relatively small. That is, the in-phase component of the ripple caused by the portion of IL that flows through the ESR “swamps out” the out-of-phase component of the ripple.
Therefore, a traditional constant-on-time power supply includes an output filter capacitor Co having an ESR that is large enough to provide a stable feedback loop.
Recently, filter capacitors having ESR values of 5 mΩ or less have become available; it is sometimes desirable to use such a low-ESR filter capacitor in a buck-converter power supply with a relatively high steady-state switching frequency to reduce the size and cost of the converter.
Unfortunately, using such a low-ESR capacitor may render a traditional constant-on-time power supply unstable. An unstable power supply may have too large of a voltage tolerance VT as described below in conjunction with FIG. 3, or may oscillate.
FIG. 3 is a plot of VOUT of FIG. 1 simulated for a 13 Ampere (A) step increase in the load current lo followed by a 13 A step decrease in lo, where VIN=10 Volts (V), Vref=1.76 V, L=1 microhenry (μH), Co=800 microfarads (μF), ESR=0, and fSW≈300 kilohertz (kH). The low value of ESR decreases the stability margin of the feedback loop, and thus causes transient “ringing” on VOUT in response to the step change in lo. Typically, a customer specifies the maximum voltage tolerance VT, which is the difference between the maximum droop of VOUT in response to a step increase in the load current lo and the maximum peak of VOUT in response to a step decrease in lo. In this example, the transient “ringing” on VOUT results in a VT of approximately 70 millivolts (mV). Because VT is inversely proportional to the value of the output filter capacitor Co, one typically chooses a value of Co large enough to provide the specified value of VT.
Some integrated-circuit (IC) manufacturers have developed constant-on-time topologies that allow the use of a low-ESR filter capacitor. But unfortunately, these topologies may require additional feedback and compensation circuitry and that the power-supply controller chip have an additional pin, and may yield a relatively poor regulation of VOUT.